The present invention relates to a method of forming a semiconductor memory cell structure having a floating gate.
A conventional structure of a flash memory will be described. FIG. 1A is a fragmentary plan view illustrative of a conventional flash memory. FIG. 1B is a fragmentary cross sectional elevation view illustrative of a conventional flash memory taken along an Axe2x80x94Axe2x80x2 line of FIG. 1A. The flash memory has an alignment of memory cells 241 which has the following structure. A floating gate 203 is formed over a gate insulation film 202 over a semiconductor substrate 201. The floating gate 203 is T-shaped which comprises an upper portion and a lower portion, wherein the upper portion laterally extends from the opposite edges of a lower portion to form the T-shaped floating gate 203. The structure of the memory cell 241 will be described in detail with reference to FIG. 1B.
Field oxide films 206 are selectively formed on a semiconductor substrate 201 to define an active region or a device region of the semiconductor substrate 201. Source and drain regions 204 and 205 are selectively formed in the active region or the device region of the semiconductor substrate 201, whereby a channel region is defined between the source and drain regions 204 and 205. A gate insulation film 202 is formed on the channel region of the semiconductor substrate 201. Source side and drain side interconnections 204a and 205a are formed on the source and drain regions 204 and 205, wherein the source side and drain side interconnections 204a and 205a are made of polysilicon films doped with an impurity. In the memory cell 241, the source and drain 204 and 205 serve as parts of bit lines. The formation of the source side and drain side interconnections 204a and 205a on and in contact with the source and drain regions 204 and 205 results in reduction in resistance of the source and drain 204 and 205. A floating gate 203 is formed which comprises an lower part and an upper part. The upper part extends laterally from the opposite edges of the lower part so that the floating gate 203 is T-shaped. The lower part of the floating gate 203 is positioned on the gate insulation film 202. Side wall oxide films 213 are formed on opposite side walls of the lower part of the floating gate 203. Insulation films 216 are formed over the field oxide films 206 and the source side and drain side interconnections 204a and 205a as well as over the side wall oxide films 213. The upper portion of the floating gate 203 extends over the lower part thereof and the insulation films 216, so that opposite edges of the upper portion of the floating gate 203 are almost aligned to the edges of the source side and drain side interconnections 204a and 205a in plane view. An insulation film 207 made of ONO is formed on the upper portion of the floating gate 203 and on the insulation films 216. A control gate 208 is formed on the insulation film 207 so that the floating gate 203 is separated and electrically floated from the control gate 208 and whereby the floating gate 203 is completely surrounded by the insulation materials to be floated in the memory cell. The control gate 208 serves as a part of a word line in the memory. The above T-shape of the floating gate increases a capacitance thereof.
The source and drain 204 and 205 are commonly used for a plurality of the memory cells 241. The drain 05 is used as a part of the bit line so that a single bit contact is formed for the plural memory cells 241 so as to allow narrowing the distance between the memory cells, thereby reducing the cell size.
The following descriptions will focus onto the fabrication method of the above flash memory. FIGS. 2A through 2H are fragmentary cross sectional elevation views illustrative of a conventional method of forming a memory cell structure over a semiconductor substrate of a flash memory shown in FIGS. 1A and 1B.
With reference to FIG. 2A, a thin insulation film 202a is formed on a surface of a semiconductor substrate 201. A bottom floating gate part 203a is selectively formed on a predetermined region of the thin insulation film 202a, wherein a film of a electrode material such as an impurity doped polysilicon is entirely formed on the surface of the semiconductor substrate 201 before patterning the same to form the bottom floating gate part 203a. The bottom floating gate part 203a is used as a mask for carrying out an ion-implantation into selected upper regions of the semiconductor substrate 201, whereby source and drain regions 204 and 205 are formed with a self-alignment technique in the selected upper regions of the semiconductor substrate 201.
With reference to FIG. 2B, the thin insulation film 202a is removed except for its underlying part which underlies the bottom floating gate part 203a, whereby the remaining underlying part of the thin insulation film 202a serves as a gate insulation film 202. An insulation film is entirely formed on the source and drain regions 204 and 205 as well as on opposite side walls and a top surface of the bottom floating gate part 203a before an etch back process using a dry etching technique so that the insulation film remain only on the opposite side walls of the bottom floating gate part 203a, whereby the side wall insulation films 213 are formed on the opposite side walls of the bottom floating gate part 203a. 
With reference to FIG. 2C, an impurity doped polysilicon film is entirely deposited over the source and drain regions 204 and 205 and the side wall insulation films 213 and the bottom floating gate part 203a. An etch back process is carried out to the impurity doped polysilicon film until the top of the bottom floating gate part 203a is shown, whereby conductive films 214 are formed on the source and drain regions 204 and 205 and positioned outside the side wall insulation films 213.
With reference to FIG. 2D, parts of the conductive films 214 on isolation regions are selectively removed. Grooves are further formed on the isolation region in the semiconductor substrate 201. An insulation material such as silicon oxide is buried within the grooves, whereby field oxide films 206 are then formed on the isolation regions. As a result, outside edges of the conductive films 214 are defined by inside boundaries of the field oxide films 206, whereby source side and drain side interconnections 204a and 205a are formed.
With reference to FIG. 2E, an insulation film 216 is entirely formed over the field oxide films 206, the source side and drain side interconnections 204a and 205a and the bottom floating gate part 203a. 
With reference to FIG. 2F, an overlying part of the insulation film 216 overlying the bottom floating gate part 203a is selectively removed by patterning the insulation film 216 with use of a photo-lithography and a subsequent dry etching technique, whereby the top of the bottom floating gate part 203a is shown.
With reference to FIG. 2G, an impurity doped polysilicon film is entirely formed which extends over the insulation films 216 and the bottom floating gate part 203a. The impurity doped polysilicon film is then patterned with a photo-lithography and a subsequent dry etching technique, whereby a top floating gate part 203b is formed which extends over the top of the bottom floating gate part 203a and inside parts of the insulation films 216 so that opposite edges of the top floating gate part 203b are aligned to outside edges of the source side and drain side interconnections 204a and 205a. As a result, a combination of the top floating gate part 203b and the bottom floating gate part 203a forms a T-shaped floating gate 203.
With reference to FIG. 2H, an insulation film 207 made of ONO is formed on the top floating gate part 203b of the floating gate 203 and on the insulation films 216. A control gate 208 is then formed on the insulation film 207 so that the floating gate 203 is separated and electrically floated from the control gate 208 and whereby the floating gate 203 is completely surrounded by the insulation materials to be floated in the memory cell.
In accordance with the above conventional fabrication processes, the floating gate comprises two parts, for example, the top floating gate part 203b and the bottom floating gate part 203a which are formed in the different steps, whereby the number of the fabrication processes are increased.
In the above circumstances, it had been required to develop a novel method of fabricating a T-shaped floating gate electrode of a memory cell in a flash memory with reduced number of the fabrication process for the T-shaped floating gate electrode.
Accordingly, it is an object of the present invention to provide a novel method of fabricating a floating gate electrode of a memory cell in a flash memory with reduced number of the fabrication process for the T-shaped floating gate electrode.
It is another object of the present invention to provide a novel floating gate electrode of a memory cell in a flash memory.
The present invention provides a floating gate memory cell structure comprising: a single pair of a first single insulation film unitary formed and a single floating gate electrode film unitary formed and laminated on the first single insulation film, the first single insulation film extending on a channel region of a semiconductor substrate and also on inside walls and top surfaces of conductive films over source and drain regions in the semiconductor substrate; a second insulation film extending on side walls and a top surface of the single floating gate electrode film; and a control electrode extending on the second insulation film so that the control electrode is separated by the second insulation film from the single floating gate electrode film.
The present invention also provides a method of forming a floating gate memory cell structure. The method comprising the following steps. A dummy pattern is selectively formed on a predetermined region of a semiconductor substrate. Source and drain regions are selectively formed by use of a self-alignment technique using the dummy pattern as a mask. Conductive films are selectively formed on the source and drain regions so that the conductive films sandwich the dummy pattern in a lateral direction. The dummy pattern is removed so that a channel region defined between the source and drain regions is shown. A first single insulation film is unitary formed, which extends on the channel region and also on inside walls and top surfaces of the conductive films. A single floating gate electrode film is unitary formed on the first single insulation film, thereby laminating a single pair of the first single insulation film unitary formed and the single floating gate electrode film unitary formed. A second insulation film is formed, which extends on side walls and a top surface of the single floating gate electrode film. A control electrode is formed, which extends on the second insulation film so that the control electrode is separated by the second insulation film from the single floating gate electrode film.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.